Delay Model Study of Single Ended Ring Oscillator (SERO)

— In this study, a new general expression for the frequency of a SERO is constructed, which includes two additional variables, K d and R w , and improves upon the traditional equations by accounting for all analysis models and various width ratios. When compared with the the conventional equations, the proposed equation is a better alternate to study the frequency response when the width ratio is concerned parameter for researchers which is addressed by the variable R w . A three stage SERO is simulated in 90 nm technology using Cadence Virtuoso platform to establish this equation. The value of K d obtained remains almost equal which justifies the reason for using this approach traditionally to calculate the delay.


I. INTRODUCTION
Voltage controlled oscillator (VCO) is an important element in the communication system and digital electronics for essential tasks such as frequency selection and clock signal generation [1,2]. Single ended ring oscillator (SERO) has been a popular choice for VCO over the inductorcapacitor (LC) oscillator because of its benefits in terms of simple manufacturability, smaller area and wider frequency tuning range [3]. A conventional SERO consists of an odd number of CMOS inverter stages as shown in Fig. 1. The load capacitances of each stage due to the MOSFET parasitics are also shown in Fig. 1. The expression of oscillating frequency in a RO is given by (1), which shows that the frequency is inversely proportional to the number of delay stages N and propagation delay tpd at each stage [4]. The propagation delay tpd is an average of the high-to-low and low-to-high propagation delays, tdHL and tdLH respectively [5]. Equation (1) can then be written as in (2).
Therefore, in order to analyze and estimate the frequency of oscillation, it is essential to correctly model the propagation delays tdHL and tdLH [6]. Two conventional methods exist to determine an approximate delay equation which analyze the CMOS inverter circuit differently. In the first method, the transistors are modelled as current sources with a constant current supply which charges and discharges the load capacitance CL [7]. In the second method, the transistor is modeled as a resistor and an equivalent RC circuit is solved for the delay expression [8]. The point at which the delay is calculated can also vary and result in a similar equation with a different coefficient value. The propagation delay can be calculated when the output is at either 50%, 90% or 100% level of the supply voltage. Although the delay is calculated at the 50% level conventionally, as shown in Fig. 2, some equations mentioned in literature [9,10] have considered the 90% and 100% levels. These analyses can lead to 5 different frequency equations for a single circuit. Moreover, the equations are based on the assumption that the PMOS to NMOS width ratio, Wp/Wn is 2. The objective of this paper is to present the analytical derivations of all these 5 equations not available in literature and, hence, derive a new general expression for the frequency of an SERO which takes into account all analysis models and different width ratios. The rest of the paper is organized as follows: section II presents the derivation of the frequency equation based on different models, section III presents the proposed general expression and simulation results are presented in section IV. Finally, section V concludes the paper while providing insight to future scope. @ Delay Model Study of Single Ended Ring Oscillator (SERO) Shourin R. Aura

A. Current Source (CS) Model 1) Delay at 50% level
As mentioned before, one way to model the propagation delay is by assuming the transistors as current sources which charge and discharge the load capacitance. The charging and discharging current equations are then given by: where, In and Ip are saturation currents of NMOS and PMOS transistors, respectively. The propagation delays tdLH and tdHL are obtained as (5) and (6). Assuming, Wp/Wn = 2 and, hence, In = Ip = Is, the resultant frequency equation is obtained in (7), where Is is the current through a single delay stage.

3) Delay at 100% level
For the 100% level, the delay is calculated when the output reaches the voltage rails, VDD or 0. In a similar method as before, the integral limits are now from 0 to VDD and VDD to 0 for equations (3) and (4), respectively. The propagation delays then obtained are given by (11) and (12) which leads to the frequency equation given by (13). This is the most common equation in literature.
f osc = I S 2NV DD C L (13)

B. RC Model
As mentioned in section 1, the inverter can also be modelled as an RC network to obtain the propagation delay. Suppose, CL is being charged to a voltage Vout from supply voltage VDD when Vin = 0, as shown in Fig. 3. The operation of the network is described by the following differential equation [11]: where, Rp is the equivalent PMOS resistance. The output expression is given by (15).

1) Delay at 50% level
For calculating delay at 50% voltage level, Vout = 0.5VDD and the expression of tdLH obtained is given by (16). Similarly for the discharging scenario, the expression of tdHL is given by (17), where Rn is the equivalent NMOS resistance.
The average on-resistances Rn and Rp can be calculated by integrating the I-V characteristic curves of the NMOS and PMOS, respectively, over the interval of interest. For example, for 50% delay calculation, the expression of Rp is given by (18) where λ is the channel length modulation constant for short channel devices. Assuming λ = 0, the approximate expressions of Rp and Rn are given by (19) Substituting equations (19) and (20) in (16) and (17), the resulting frequency equation is given by (21) where Is = In = Ip, assuming Wp/Wn = 2.   Note that, using the RC model, the delay cannot be calculated at the 100% voltage level as the value of tdLH from (15) evaluates to 0.

III. PROPOSED GENERAL EQUATION
The objective of this work is to present all 5 equations discussed above into one single equation while addressing the variable Wp/Wn ratio in the expression. Let Wp = RwWn, where Rw is the PMOS transistor to NMOS transistor width ratio. Since the frequency equations consist of the current Is, a relation between In and Ip in terms Rw needs to be developed. Ideally when Rw = 2, In = Ip = Is, and when Rw = 1, In = 2Ip. This is due to the difference in mobility of electrons and holes in NMOS and PMOS, respectively. Therefore, the relation between In and Ip is given by (27).
Using this relation with the CS model and 50% delay calculation procedure, the high-to-low and low-to-high propagation delays obtained are given by: The summation of the two delays, td is given by equation (30).
Using equation (30), the expression of oscillating frequency for the 50% CS model is given by (31) where, Kd is the coefficient of delay model and Is is the source current. Kd is 0.5 in this case. Since, Ip is directly the current from the supply, Ip can be replaced with Is.
Similarly, the relation in (27) can be used for the remaining 4 models to obtain the same expression in (31) for the frequency but with different Kd value. The value of coefficient for the 5 different models are presented in Table  I.

IV. SIMULATION RESULTS
A three stage SERO with load capacitances is simulated in 90 nm technology using Cadence Virtuoso platform. The supply voltage is varied between 0.3 V and 2 V. The value of the load capacitance is calculated using the equation in [12]. The circuit is first simulated with Rw = 2 and the new equation is compared with the conventional equations. The percentage of error between the proposed and existing equations for all values of VDD, as given in Table II, shows that the proposed expression obtains the same result as the conventional equations when the width ratio is 2.
The circuit is re-simulated with Rw = 0.33 where Wn = 360 nm and Wp = 120 nm. The simulated frequency response is then compared with both conventional and proposed equation for all different models. The frequency-voltage characteristics shown in Fig. 4 proves that the proposed equation gives a better estimation (71% improvement) of the frequency since it addresses the changed width ratio.

V. CONCLUSIONS AND FUTURE SCOPES
The analytical frequency equation of an SERO can be obtained through various approaches leading to different results. The conventional methods also assume the ideal value of 2 for the PMOS to NMOS width ratio. A new general expression is proposed in this paper which introduces two new variables Kd and Rw. The value of Kd is given in Table  1 for different delay models which may be chosen for the frequency estimation. The variable Rw addresses the effect of PMOS to NMOS width ratio on the frequency and provides 71% improvement than the conventional equations. Therefore, the proposed equation is a better alternate to the conventional equations to study the frequency response when the width ratio is concerned parameter for researchers. Using the 50% delay calculation for both CS and RC models, the value of Kd obtained remains almost equal which justifies the reason for using this approach traditionally to calculate the delay. In future, the effectiveness of the equation can be studied for more different width ratios and technologies. Although the proposed equation proves to be a better alternative, the percentage of errors with the simulated frequency response remain very high. This is because the current and load capacitance were assumed constant, though they are both voltage dependent. The MOSFETs' region of operation also changes during one voltage swing which changes the expressions of current and equivalent resistance. The current and load capacitance also need to be simulated and calculated, respectively, to estimate the frequency which makes the equation futile for designers. A more accurate, while simple, frequency equation needs to be derived in future for reliable study of the RO frequency response.