Design and Implementation of MIPS Processor for LU Decomposition based on FPGA



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Submitted Apr 14, 2020
Published May 21, 2020
10.24018/ejece.2020.4.3.209

Abstract viewed = 396 times

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The solution for a set of liner equations require to find the matrix inverse of a square matrix with same number of the linear equations, this operation require many mathematical calculations. To solve this problem, LU decomposition for the matrix is used, which computes two matrices, a lower triangle matrix and an upper triangle matrix. In this, paper a design for 32-bits MIPS (microprocessor without interlocked pipelined stages) processor with the required instructions that used to calculate the LU matrices. The design implemented using VHDL (Very high speed integrated circuit hardware description language) then integrated with FPGA (Field Programmable Gate Arrays) Xilinx Spartan 6. The results for the different parts of the processor are resented in the form of test bench waveform and the architecture of the system is demonstrated and the results was matched with theoretical results.

Keywords: Field Programmable Gate Array (FPGA), LU decomposition, VHDL, MIPS Processor.

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